AS7C31026B-12TCN

The AS7C31026B-12TCN is a 3.3V 64k x 16-bit high-performance CMOS Static Random Access Memory (SRAM) device organized as 65536 words x 16-bit. It is designed for memory applications where fast data access, low power and simple interfacing are desired. A write cycle is accomplished by asserting write enable and chip enable. Data on the input pins I/O0 through I/O15 is written on the rising edge of WE or CE. To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable or write enable. A read cycle is accomplished by asserting output enable and chip enable with write enable high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins and separate byte enable controls, allowing individual bytes to be written and read.

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