The dsPIC33F Digital Signal Controllers offer the performance of a DSP with the simplicity of an MCU. The 40MIPS dsPIC33F core is designed to execute digital filter algorithms, high-speed precision digital control loops and digital audio and speech processing.
dsPIC33F DSCs with Motor Control peripherals enable the design of high-performance, precision motor control systems. The dsPIC33F SMPS DSCs provide on-chip peripherals specifically designed for high-performance, digital power supplies. SMPS peripherals include high speed and high resolution PWM, fast ADC and analogue comparators.
Feature
- Operating Range:
- Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
- High-Performance DSC CPU:
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit-wide data path
- 24-bit-wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly one word/one cycle
- Two 40-bit accumulators with rounding and saturation options
- Flexible and powerful addressing modes:
- Software stack
- 16 x 16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate: Up to ±16-bit shifts for up to 40-bit data
- Timers/Capture/Compare/PWM:
- Timer/Counters, up to three 16-bit timers
- Input Capture (up to four channels)
- Output Compare (up to two channels)
- Interrupt Controller:
- 5-cycle latency
- Up to 26 available interrupt sources
- Up to three external interrupts
- Seven programmable priority levels
- Four processor exceptions
- Digital I/O:
- Peripheral pin Select functionality
- Up to 21 programmable digital I/O pins
- Wake-up/Interrupt-on-Change for up to 21 pins
- Output pins can drive from 3.0V to 3.6V
- Up to 5V output with open drain configurations on 5V tolerant pins
- 4 mA sink on all I/O pins
- On-Chip Flash and SRAM:
- Flash program memory (12 Kbytes)
- Data SRAM (1024 bytes)
- Boot and General Security for program Flash System Management:
- Flexible clock option
- Power-up Timer
- Oscillator Start-up Timer/Stabilizer
- Watchdog Timer with its own RC oscillator
- Fail-Safe Clock Monitor
- Reset by multiple sources
- Power Management:
- On-chip 2.5V voltage regulator
- Switch between clock sources in real time
- Idle, Sleep, and Doze modes with fast wake
- Motor Control Peripherals:
- 6-channel 16-bit Motor Control PWM
- Quadrature Encoder Interface module
- Analog-to-Digital Converters (ADCs):
- 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- -Two and four simultaneous samples (10-bit ADC)
- -Up to six input channels with auto-scanning
- CMOS Flash Technology:
- Low-power, high-speed Flash technology
- Fully static design
- 3.3V (±10%) operating voltage
- Industrial and Extended temperature
- Low power consumption
- Communication Modules:
- 4-wire SPI:
- -Framing supports I/O interface to simple codecs
- - Supports 8-bit and 16-bit data
- -Supports all serial clock formats and sampling modes
- I2C™:
- - Full Multi-Master Slave mode support
- - 7-bit and 10-bit addressing
- - Bus collision detection and arbitration
- - Integrated signal conditioning
- - Slave address masking
- UART:
- - Interrupt on address bit detect
- - Interrupt on UART error
- - Wake-up on Start bit from Sleep mode
- - 4-character TX and RX FIFO buffers
- - LIN bus support
- - IrDA® encoding and decoding in hardware
- - High-Speed Baud mode
- - Hardware Flow Control with CTS and RTS
