Xilinx® Defense-grade 7 series FPGAs comprise three FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the high reliability requirements beyond commercial applications. The Defense-grade 7 series FPGAs include:
- Artix®-7Q Family: Optimized for lowest cost and power with small form-factor packaging for the highest volume applications.
- Kintex®-7Q Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.
- Virtex®-7Q Family: Optimized for highest system performance and capacity with a 2X improvement in system performance.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, Defense-grade 7 series FPGAs enable an unparalleled increase in system performance with 1.4 Tb/s of I/O bandwidth, 980K logic cell capacity, and 4.7 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Feature
- Full-range extended temperature testing
- Mask set control
- Fully leaded (Pb) content
- Ruggedized packaging
- Long-term availability
- Anti-counterfeiting features
- 4th Generation Information Assurance and Anti-tamper support
- Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
- 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
- High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
- High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 11.3 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
- A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.
- DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high performance filtering, including optimized symmetric coefficient filtering.
- Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
- Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
- Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
- Wire-bond and high signal integrity lidded flip-chip ruggedized packages offering easy migration between family members in the same package. All packages are available in Pb option.
- Designed for high performance and lowest power with 28 nm, HKMG, and HPL process.
