are implemented in a silicon gate, twolevel metal CMOS process, uillizng Actel's PLICE antifuse technology. Thisunique architecture offers gate array flexibility, high performance, and quick turnaround through user progr amming, Device utilization is typically 95 percent of ailable logic modules.
Feature
●Highly Predictable Performance with 100 Percent Automatic Placement and Routing
●Device Sizes from 1200to 20,000 gates
●Up to6, Fast, Low-Skew Clock Networks
●Up to 202 User-Programmable I/0 Pins
●More Than 500 Macro Functions
●Up to 1276 Dedicated Flip-Flops
●/ODrive to 10 mA ,
●Devices Available to DSCC SMD
●CQFP and CPGA Packaging
●Nonvolatile, User Progr ammable
●Logic Fully Tested Prior to Shipment
ACT 3 Features
●Highest-Performance, Higest-Capacity FPGA Family
●System Performance to 60 MHz over Military Temperature
●Low-Power 0.8-micron CMOS Technology
●Device Sizes from 1200to 20,000 gates
●Up to6, Fast, Low-Skew Clock Networks
●Up to 202 User-Programmable I/0 Pins
●More Than 500 Macro Functions
●Up to 1276 Dedicated Flip-Flops
●/ODrive to 10 mA ,
●Devices Available to DSCC SMD
●CQFP and CPGA Packaging
●Nonvolatile, User Progr ammable
●Logic Fully Tested Prior to Shipment
ACT 3 Features
●Highest-Performance, Higest-Capacity FPGA Family
●System Performance to 60 MHz over Military Temperature
●Low-Power 0.8-micron CMOS Technology
