■ Flash memory
– Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications
– 5-signal communication interface supporting Read and Write operations
– 5 additional general-purpose inputs for platform design flexibility
– Synchronized with 33 MHz PCI clock
■ 16 blocks of 64 Kbytes
– 13 blocks of 64 Kbytes each
– 3 blocks, subdivided into 16 uniform
sectors of 4 Kbytes each Two blocks at the top and one at the bottom (M50FLW080A)
One block at the top and two at the bottom (M50FLW080B)
■ Enhanced security
– Hardware Write Protect pins for block protection
– Register-based Read and Write Protection
– Individual Lock Register for each 4 KByte sector
■ Supply voltage
– VCC = 3.0 to 3.6 V for Program, Erase and Read operations
– VPP = 12 V for Fast Program and Erase
■ Two interfaces
– Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) memory cycles for embedded operation with PC chipsets
– Address/Address Multiplexed (A/A Mux) interface for programming equipment compatibility.
■ Programming time: 10 µs typical
■ Program/Erase Controller
– Embedded Program and Erase algorithms
– Status Register bits
■ Program/Erase Suspend
– Read other Blocks/Sectors during Program Suspend
– Program other Blocks/Sectors during Erase Suspend
■ ELectronic signature
– Manufacturer Code: 20h
– Device Code (M50FLW080A): 80h
– Device Code (M50FLW080B): 81h
■ Packages
– ECOPACK® (RoHS compliant)
(Picture: Pinout)
