This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.
Feature
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
- Low Static-Power Consumption (ICC = 0.9 μA Max)
- Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
- Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise Overshoot and Undershoot <10% of VCC
- Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typical at 3.3 V)
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.8 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
This single 2-input positive-NAND gate performs the Boolean function Y = B in positive logic.
