(1) Additional temperature ranges available - contact factory
DescriptionThis single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 has an asynchronous clear (CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Feature
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.3 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial Power-Down-Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Military (–55°C/125°C) Temperature Range(1)
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
(1) Additional temperature ranges available - contact factory
DescriptionThis single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 has an asynchronous clear (CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
