The 74LVC2G34GW,125 is a dual Buffer Gate fully specified for partial power-down applications using IOFF. Inputs can be driven from either 3.3/5V devices. These features allow the use of these devices in a mixed 3.3 and 5V environment. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Feature
- High noise immunity
- CMOS low-power consumption
- Direct interface with TTL levels
- Complies with JEDEC standard
- 5V Tolerant input/output for interfacing with 5V logic
- Latch-up performance exceeds 250mA
- ±24mA Output drive