The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.
The flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
Applications- Communications
- Diversity radio systems
- Multimode digital receivers (3G and 4G)GSM, EDGE, W-CDMA, LTE,CDMA2000, WiMAX, TD-SCDMA
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
Feature
- JESD204A coded serial digital outputs
- SNR = 73.7 dBFS @70 MHz and 80MSPS
- SNR = 72.8 dBFS @70 MHz and 155MSPS
- SFDR = 94 dBc @ 70 MHz and 80 MSPS
- SFDR = 90 dBc @ 70 MHz and 155 MSPS Low power: 238 mW @ 80 MSPS 1.8 V supply operation
- Low power: 238 mW @ 80 MSPS, 313mW at 155 MSPS
- 1.8 V supply operation
- Integer 1-to-8 input clock divider
- IF sampling frequencies to 250 MHz
- Please see data sheet for additional features
